This invention relates to thin-film transistors and to methods for producing the same. More particularly, the invention relates to staggered thin film transistors and production methods for such transistors, having self-aligned gate structures with an overlap between the gate and the source and drain electrodes. Such thin-film transistors are suitable for use in flat panel display devices, for example active-matrix liquid-crystal displays, or in other large-area electronic devices.
Various methods have been proposed for defining self-aligned gate structures in thin film transistors. In some of these methods, the gate conductor has a width which is smaller than the spacing between the source and drain electrodes. This provides some freedom in the positioning of the insulated gate structure with respect to the source and drain electrode structure. However, the regions of the semiconductor body of the transistor between the gate and source/drain electrodes then require treatment to reduce the transistor contact resistances. Various processes have been proposed for this purpose. Typically, these processes involve laser crystallisation and/or ion implatation of those regions of the semiconductor layer. The gate structure plays a part in these processes to maintain the self-aligned property.
This additional treatment adds processing steps and thereby increases the complexity of the manufacturing process. It has been recognised that the need or treatment of the semiconductor layer to reduce the resistance can be avoided if an overlap is provided between the gate electrode and the source and drain electrodes. In this way, the gate modulates the full semiconductor channel area. However, the degree of overlap dictates the capacitance between the gate and the source and drain electrodes, which in turn influences the transistor switching characteristics. When thin film transistors are used in array devices, uniformity of the transistor response characteristics is critical, and consequently the degree of overlap needs to be accurately controllable.
One proposed method for providing a self-aligned thin film transistor with an overlap provided between the gate conductor and the source and drain conductors involves the use of through-the-substrate exposure of a photoresist layer. For example, in the case of a top gate structure, UV light passes through the opening between the opaque source and drain regions and diffracts and scatters through the structure before reaching the photoresist layer. This results in some gate to source/drain overlap, so that the full channel width is modulated by the gate conductor patterned using the selectively exposed resist layer. However, the degree of overlap of the gate conductor with respect to the source and drain conductors is not accurately controllable and may not be sufficient to provide satisfactory operating characteristics of the thin film transistor.
U.S. Pat. No. 5,156,986 describes a bottom-gate transistor configuration in which the source and drain electrodes are self-aligned with the gate electrode, but overlap the edges of the gate. One proposed method in U.S. Pat. No. 5,156,986 for achieving this involves the use of through-the-substrate exposure of a positive photoresist layer to enable a masking plug to be formed prior to deposition of the top source and drain electrode layers. A two-layer gate conductor is disclosed comprising a transparent layer and an opaque layer, with the opaque layer only being used to define the shape of the masking plug. The spacing between the source and drain electrodes is eventually defined by a non-selective uniform etching of the entire structure, until the source/drain metallisation is exposed over the masking plug, as a result of its greater height in that region. The spacing between the gate and source of this structure is therefore determined by the contours of the various layers defining the entire structure, and also depends upon the exact point at which the non-selective etching is halted. Consequently, device characteristics may vary between different transistors depending upon local variations in these parameters.
The present invention provides a method of forming a thin film transistor comprising:
providing first electrode layers over a transparent substrate, the first electrode layers comprising a lower transparent layer, and an upper opaque layer;
patterning the first electrode layers to define a first electrode pattern in which an edge region of the transparent layer extends beyond an edge region of the opaque layer;
providing a transistor body comprising a semiconductor layer defining the channel area of the transistor and a gate insulator layer;
providing a transparent second electrode layer;
providing a layer of negative resist over the second electrode layer;
exposing the layer of negative resist through the substrate such that regions of the negative resist layer shadowed by the opaque layer of the first electrode pattern remain unexposed; and
removing the unexposed negative resist and the underlying second electrode layer to define a second electrode pattern which is substantially aligned with the opaque layer of the first electrode pattern.
In addition, according to the present invention there is provided a method of forming a thin film transistor comprising:
providing first electrode layers over a transparent substrate, the first electrode layers comprising a lower transparent layer, and an upper opaque layer;
patterning the first electrode layers to define a first electrode pattern in which an edge region of the transparent layer extends beyond an edge region of the opaque layer;
providing a transistor body region over the first electrode pattern, the transistor body region comprising a semiconductor layer defining the channel area of the transistor and a gate insulator layer;
providing a transparent second electrode layer over the transistor body region;
providing a layer of negative resist over the second electrode layer;
exposing the layer of negative resist through the substrate such that regions of the negative resist layer shadowed by the opaque layer of the first electrode pattern remain unexposed;
removing the unexposed negative resist and the underlying second electrode layer to define a second electrode pattern which is substantially aligned with the opaque layer of the first electrode pattern.
The method of the invention uses through-the-substrate exposure of negative resist in order to define the subsequent patterning of the upper electrode layer of the transistor structure. The exposure of the negative resist layer depends upon the shape of the opaque layer of the lower, first electrode layers. The transparent layer of the lower, first electrode layers ensures that there is overlap between the gate conductor and the source and drain conductors of the transistor.
The method may be employed for forming a bottom gate or top gate thin film transistor. One of the first and second electrode layers will define the gate conductor, and the other will define the source and drain electrode pattern. A channel etched or etch stop structure may be defined. Furthermore, coplanar bottom or top gated structures may be formed.
Patterning of the first electrode layers preferably comprises etching, for example wet etching, using an etchant which etches the lower transparent layer and the upper opaque layer at different rates. The etching time may then be selected to produce a desired degree of overlap by which the edge region of the transparent layer extends beyond the edge region of the opaque layer. This degree of overlap in turn determines the overlap of the source and drain electrodes with respect to the gate electrode, and thereby determines the operating characteristics of the transistor.
The invention also provides a thin film transistor comprising:
a first electrode pattern provided over a substrate, the first electrode pattern comprising a lower transparent layer, and an upper opaque layer, an edge region of the transparent layer extending beyond an edge region of the opaque layer; a transistor body comprising a semiconductor layer defining the channel area of the transistor and a gate insulator layer; and a transparent second electrode pattern substantially aligned with the opaque layer of the first electrode pattern.
Furthermore, the present invention provides a thin film transistor comprising:
a first electrode pattern provided over a substrate;
a transistor body region provided over the first electrode pattern, the transistor body region comprising a semiconductor layer defining the channel area of the transistor and a gate insulator layer; and
a second electrode pattern over the transistor body region, wherein the first electrode pattern comprises a lower transparent layer, and an upper opaque layer, an edge region of the transparent layer extending beyond an edge region of the opaque layer, in that the second electrode pattern is transparent, and in that the second electrode pattern is substantially aligned with the opaque layer of the first electrode pattern.
The transistor of the invention is suitable for manufacture using the method above. The transistor may be used in an electronic device, for example a liquid crystal display which will include a transistor substrate comprising an array of the thin film transistors.